1. Field of the Invention
The present invention generally relates to semiconductor memory devices and, more particularly, the present invention relates to method of programming a flash memory device and to a method of enabling a word line of a flash memory device.
A claim of priority under 35 U.S.C § 119 is made to Korean Patent Application 2005-109999 filed on Nov. 17, 2005, the entire contents of which are hereby incorporated by reference.
2. Description of the Related Art
A flash memory device, known as a flash EEPROM (electrically erasable programmable read-only memory), typically includes an array of memory cells formed of floating gate transistors. In a NAND-type flash memory device, the array includes strings (or, “NAND strings”) of series connected the floating gate transistors, with each NAND string being connected in series between a string selection transistor and a ground selection transistor. A plurality of word lines intersect the NAND strings and are connected to the control gates of corresponding floating gate transistors.
In an initial erased state, the floating gate transistors, i.e., memory cells, have a lower threshold voltage (e.g. −3V). To program a given memory cell, a high voltage (e.g., 20V) is applied to the word line of a selected memory cell for a predetermined period of time to cause the selected memory cell to have higher threshold voltage. Meanwhile, the threshold voltages of unselected memory cells do not change.
A potential problem arises when programming the selected memory cell. That is, when a program voltage is applied to the word line of the selected memory cell, the same voltage is also applied to the unselected memory cells connected along the same word line. Thus, the unselected memory cells connected to the word line, and in particular, the memory cell or cells adjacent to the selected memory cell may unintentionally be programmed. Such unintentional programming of one or more unselected memory cells is referred to as “program disturb”.
A conventional method utilized in an attempt to prevent the problem of program disturb is known as a program inhibition method employing a self-boosting scheme. The program inhibition method employing the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “Method of Programming Flash EEPROM Integrated Circuit Memory Devices To Prevent Inadvertent Programming of Nondesignated NAND Memory Cells Therein”, and U.S. Pat. No. 5,991,202 entitled “Method for Reducing Program Disturb During Self-Boosting in a NAND Flash Memory”, which are incorporated herein by reference.
In the program inhibition method using the self-boosting scheme, a ground path is blocked by applying 0V to the gate of a ground selection transistor. 0V is applied to a selected bit line, while a power supply voltage Vcc of 3.3V or 5V is applied as a program inhibition voltage to an unselected bit line. At the same time, after the source of a string selection transistor is charged to Vcc-Vth (Vth: a threshold voltage of the string selection transistor) by applying the power supply voltage to the gate of the string selection transistor, the string selection transistor is virtually blocked. A channel voltage of the program inhibited cell transistor is then boosted by applying the program voltage Vpgm to the selected word line, and pass voltage Vpass to the unselected word lines. Thus, Fowler-Nordheim (F-N) tunneling cannot take place between the floating gate and the channel, thereby keeping the program inhibited cell transistor in the initial erased state.
In the conventional program inhibition methods utilizing the self-boosting scheme, a problem arises as the density of the flash memory device is increased. That is, as the integration density is increased, the intervals between adjacent signal lines are reduced, thereby increasing the possibility of coupling between the adjacent signal lines.
As a result, for example, when a memory cell adjacent to the string selection transistor is programmed, the voltage on the string selection line (e.g., the power supply voltage) may be boosted as a result of capacitive coupling with the word line when the program voltage is applied to the selected word line. The rising voltage of the string selection line can cause the string selection transistor to turn on, which in turn can cause charges in the channel of the program inhibited cell transistor to go out to the unselected bit line through the string selection transistor. This can result in a soft programming of the program inhibited cell transistor due to a reduction of the channel voltage of the program inhibited cell transistor.
Also, when the pass voltage is applied as a high voltage to a word line adjacent to the string selection line, the voltage on the string selection line (e.g., the power supply voltage) may be boosted due to capacitive coupling with the word line. The resultant rising voltage of the string selection line can turn on the string selection transistor, which can cause charges in the channel of the program inhibited cell transistor to go out to the unselected bit line through the string selection transistor. Again, this can result in a soft programming of the program inhibited cell transistor due to a reduction of the channel voltage of the program inhibited cell transistor.
Further, when the program voltage is applied to the selected word line, the pass voltage of an unselected word line is boosted due to the program voltage of the selected word line. This too can result in soft programming of memory cells of the unselected word line.